AOC2800 vss 30v i d (at v gs =4.5v) 6a r ss(on) (at v gs =4.5v) < 42m w r ss(on) (at v gs =4.0v) < 44m w r ss(on) (at v gs =3.1v) < 49m w r ss(on) (at v gs =2.5v) < 61m w the AOC2800 uses advanced trench technology to prov ide excellent r ss(on) , low gate charge and operation with gate voltages as low as 2.5v while retaining a 12v v gs(max) rating. it is esd protected. this device is suitable for us e as a uni- directional or bi-directional load switch, facilita ted by its common-drain configuration. equivalent circuit top view bottom view wlcsp 1.57x1.57_4 symbol v ss v gs t a =25c i s i sm p d t j , t stg note 1. mounted on minimum pad pcb note 2. pw <300 s pulses, duty cycle 0.5% max units source-source voltage source current (dc) note1 6 v v w junction and storage temperature range a 1.3 -55 to 150 60 power dissipation note1 t a =25c c maximum parameter absolute maximum ratings t a =25c unless otherwise noted 12 30 source current (pulse) note2 gate-source voltage g2 g1 s1 pin1(s1) s2 g1 g2 d1 s1 d2 s2 common-drain dual n-channel enhancement mode field effect transistor general description features www.freescale.net.cn 1 / 5
symbol min typ max units bv sss 30 v 1 t j =55c 5 i gss 1 10 bv gso 12 v v gs(th) 0.5 1 1.5 v 35 42 t j =125c 53 63 37 44 41 49 49 61 g fs 21 s v fss 0.7 1 v c iss 984 1180 pf c oss 93 pf c rss 57 pf r g 1.5 k w t d(on) 320 ns t r 800 ns t d(off) 3.8 m s t f 3.6 m s q g 9.1 nc note: pulsed this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising m a i sss v gs =2.5v, i s =3a, test circuit 4 v gs =4.5v, i s =3a, test circuit 4 gate-source breakdown voltage v ss =0v, i g =250 m a, test circuit 7 static source to source on-resistance note gate threshold voltage static parameters parameter conditions electrical characteristics (t j =25c unless otherwise noted) source-source breakdown voltage i s =250 m a, v gs =0v, test circuit 6 zero gate voltage source current gate leakage current forward transconductance note r ss(on) v ss =v gs i s =250 m a, test circuit 3 v ss =20v, v gs =0v, test circuit 1 v ss =0v, v gs = 10v, test circuit 2 v gs =3.1v, i s =3a, test circuit 4 i s =1a,v gs =0v, test circuit 5 v ss =5v, i s =3a, test circuit 3 dynamic parameters v gs =4.0v, i s =3a, test circuit 4 diode forward voltage note m w total gate charge v g1s1 =4.5v, v ss =15v, i s =6a turn-off fall time input capacitance output capacitance turn-on delaytime turn-on rise time turn-off delaytime reverse transfer capacitance gate resistance v gs =10v, v ss =15v, r l =2.4 w , r gen =6 w , v gs =0v, v ss =15v, f=1mhz, switching parameters v gs =0v, v ss =0v, f=1mhz components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice AOC2800 common-drain dual n-channel enhancement mode field effect transistor www.freescale.net.cn 2 / 5
typical electrical and thermal characteristics 0 10 20 30 40 50 60 0 1 2 3 4 5 i s (a) v ss (volts) fig 1: on-region characteristics v gs =2v 3v 2.5v 3.5v 4.5v 4v 0 4 8 12 16 20 1 1.25 1.5 1.75 2 2.25 2.5 i s (a) v gs (volts) figure 2: transfer characteristics 30 35 40 45 50 55 60 65 70 75 0 5 10 15 20 r ss(on) (m w w w w ) 0.8 1 1.2 1.4 1.6 0 25 50 75 100 125 150 175 normalized on-resistance v gs =2.5v v gs =3.1v v gs =4v v gs =4.5v 25 c 125 c v ss =5v v gs =2.5v v gs =4.5v v gs =3.1 -25 c 75 c v gs =4v 30 0 5 10 15 20 i s (a) figure 3: on-resistance vs. drain current and gate voltage 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.0 0.5 1.0 1.5 2.0 2.5 i s (a) v ss (volts) figure 6: body-diode characteristics 25 c 125 c - 25 c 75 c 0.8 0 25 50 75 100 125 150 175 temperature (c) figure 4: on-resistance vs. junction temperature 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 r ss(on) (m w w w w ) v gs (volts) figure 5: on-resistance vs. gate-source voltage i s =3a 25 c 125 c AOC2800 common-drain dual n-channel enhancement mode field effect transistor www.freescale.net.cn 3 / 5
typical electrical and thermal characteristics 0 1 2 3 4 5 6 0 2 4 6 8 10 12 14 v gs (volts) q g (nc) figure 7: gate-charge characteristics 0 200 400 600 800 1000 1200 1400 0 5 10 15 20 25 30 capacitance (pf) v ss (volts) figure 8: capacitance characteristics c iss 10 20 30 40 50 power (w) c oss c rss v ss =15v i s =6a t j(max) =150 c t a =25 c 0.1 1.0 10.0 100.0 i s (amps) 10 m s 10ms 1ms 1s dc r ss(on) limited t j(max) =150 c t a =25 c 100 m s 100ms 0 10 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 10: single pulse power rating junction-to- ambient (note e) 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 z q q q q ja normalized transient thermal resistance pulse width (s) figure 11: normalized maximum transient thermal imp edance single pulse d=t on /(t on +t) t j,pk =t a +p d .z q ja .r q ja r q ja =100 c/w t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse 0.0 0.1 0.01 0.1 1 10 100 v ss (volts) figure 9: maximum forward biased safe operating area (note e) 1s t j(max) =150 c t a =25 c 100ms AOC2800 common-drain dual n-channel enhancement mode field effect transistor www.freescale.net.cn 4 / 5
test circuit 1 isss test circuit 1 isss test circuit 1 isss test circuit 1 isss test circuit 2 igss1,2 test circuit 2 igss1,2 test circuit 2 igss1,2 test circuit 2 igss1,2 positive vss for isss+ positive vgs for igss1+ negative vss for isss- negative vgs for igss1- when fet1 is measured between gate and source of fet2 are shorted test circuit 3 vgs test circuit 3 vgs test circuit 3 vgs test circuit 3 vgs ( (( ( off off off off ) )) ) test circuit 4 rss test circuit 4 rss test circuit 4 rss test circuit 4 rss ( (( ( on onon on ) )) ) when fet1 is measured vss/is between gate and source of fet2 are shorted test circuit 5 v test circuit 5 v test circuit 5 v test circuit 5 v f(ss)1,2 f(ss)1,2 f(ss)1,2 f(ss)1,2 test circuit 6 bv test circuit 6 bv test circuit 6 bv test circuit 6 bv dss dss dss dss positive vss for isss+ negative vss for isss- g2 d2 s2 g1 d1 s1 a vss vg g2 d2 s2 g1 d1 s1 a g2 d2 s2 g1 d1 s1 a vgs vss is g2 d2 s2 g1 d1 s1 v vgs vss s2 4.5v s2 when fet1 measured fet2 v gs=4.5v test circuit 7 bv test circuit 7 bv test circuit 7 bv test circuit 7 bv gso1,2 gso1,2 gso1,2 gso1,2 positive vss for isss+ negative vss for isss- when fet1 is measured between gate and source of fet2 are shorted i f g2 d2 g1 d1 s1 v vgs=0 vss is g2 d2 g1 d1 s1 v g2 d2 s2 g1 d1 s1 v i g AOC2800 common-drain dual n-channel enhancement mode field effect transistor www.freescale.net.cn 5 / 5
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